wafer.space Community

kris

a ceramic package would be so pretty (edited)

And expensive!

1

how much does it compare to the other packages?

I've seen prices like O($100) USD per package

ooh ouch

2:26 a.m.

time to buy a kiln and make some casts lol

I wonder if that is a real thing

ReJ aka Renaldas Zioma

I wonder if that is a real thing

Kinda looks like reclaimed device?

leadframe looks intact to me

2

Tim 'mithro' Ansell

Kinda looks like reclaimed device?

imho should be new (edited)

1

what is that part?

kris

what is that part?

I dunno, but I saw them on the other photos with new ceramic packages. Perhaps something that is used to hold them while bonding. (edited)

5:11 p.m.

Maybe just part of the manufacturing process (edited)

Yes exactly, after bonding it gets snipped off

1

ohh that’s interesting, the holes in the first one make it look like it can be daisy chained with other ones

I think it normally is… it comes as a continuous strip. The one pictured has already been snipped off the strip.

12:50 p.m.

(I think)

I've seen them come in large metal panels.

Hey all, Just got some PCBs back today for prototyping and verification. edit: also note these are HASL, while real versions will be ENIG. It didn't seem worth $75 for just pictures (edited)

3:00 a.m.

I will try and assemble a few tomorrow no die, just mezzanine connectors and headers

3:04 a.m.

Mezzanine connectors also arrived today.

3:11 a.m.

Last night I also played for a few minutes with another layout for the wirebonders. This would also fit into a dip package layout.

1

3:11 a.m.

Andrew Wingate

Mezzanine connectors also arrived today.

Delightful

I’m getting excited!

1

Andrew Wingate

Click to see attachment 🖼️

Diplightful!

2

Andrew Wingate

Last night I also played for a few minutes with another layout for the wirebonders. This would also fit into a dip package layout.

Great news!

Andrew Wingate

Click to see attachment 🖼️

Is there a minimum distance requirement between the chip and the binding pad on a PCB? I am thinkng about 0.5x1 chip but rotate 90 degrees for placement.

I think 1.5x~2x the die thickness IIRC.

ReJ aka Renaldas Zioma

Is there a minimum distance requirement between the chip and the binding pad on a PCB? I am thinkng about 0.5x1 chip but rotate 90 degrees for placement.

Yes @tnt you are correct https://drive.google.com/file/d/1touEQHWAOTon_98TdiVLKKqsQ8RJJ1tP/view

Design Rule SCMicro .pdf

What is the expected thickness of the die?

The ones I have are about 0.7mm

Although the numbers here are way off. IIRC the chips won't be back grinded so it'll be more like 800 um if it's anything like the sky130/ihp ones.

I also believe they will not be back grinded

8:28 a.m.

What I drew above is pushing pretty close to the limits in spots

@Andrew Wingate btw, those light blue outgoing lines? They don't (always) connect to the red pads. Are these the ideal wire "diretions"?

ReJ aka Renaldas Zioma

@Andrew Wingate btw, those light blue outgoing lines? They don't (always) connect to the red pads. Are these the ideal wire "diretions"?

I spent maybe 10 minutes on this. Just sharing for the sake of sharing. The lines you see are just the old lines from the old version and don't really mean anything

1

8:32 a.m.

Also @ReJ aka Renaldas Zioma When you all are saying DIP, what width DIP are you referring to?

Andrew Wingate

Also @ReJ aka Renaldas Zioma When you all are saying DIP, what width DIP are you referring to?

8:34 a.m.

This one

The wide version that's .6" between centers

2

8:34 a.m.

haha ok yeah!!

8:34 a.m.

Thank you

inches are hard!

2

12:19 a.m.

3

Forgive the fact this is LTT, but this one is a factory tour of a fab, touches on packaging and a bunch of other steps we're working on. I thought it was pretty cool https://www.youtube.com/watch?v=ivLvsTnp9fI

Linus Tech Tips

A Petabyte in the Palm of My Hand - Kioxia Factory Tour

I really enjoyed that video. better than the recent hisense tour, and even better than the intel video.

5:19 a.m.

It probably won’t be a great performer for LMG, but that doesn’t matter—it’s still cool

1

Just assembled the first test COB. I think I pretty much like the form factor. With 70pins they hold on there pretty good. Some conversations with other people, they had mentioned mezzanine connectors to the a weak point, but these seem pretty solid. I think I'm pretty happy with them overall.

4

I love the small metallic rocket in the corner!

1

ReJ aka Renaldas Zioma

I love the small metallic rocket in the corner!

On the real ones it will be gold colored

2

1

looks amazing

2

I soldered some headers on and put it on a breadboard. It's a little on the large size, but should work great if you need it.

4

I see the PDK has rules for bumping, is that a thing we could get from GF in the future? https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4.html

1

BreakingTaps

I see the PDK has rules for bumping, is that a thing we could get from GF in the future? https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_09_4.html

I have also brought up WCSP before. It seems there are a few issues. 1. Just the extra cost, it would require more masks and processes. 2. It seems the people who do the bumping are not interested in the quantities we're doing. 3. Everyone would have to agree on a standard pinout. (I don't see this one as a dealbreaker, but poses some issues when we try to subdivide dies into smaller forms, or probably worse going in the other direction for a larger than standard size like you were asking for for more sram.) It certainly is something that would be very useful if we can devise a way to make it work under all these constraints.

makes sense, thanks @Andrew Wingate! was contemplating chiplet'y things to get more SRAM and simple "bridge" interposers using bumps was a potential candidate

1

Andrew Wingate

I soldered some headers on and put it on a breadboard. It's a little on the large size, but should work great if you need it.

It's very long

asic destroyer

It's very long

It is, but it's also all 70 pins

It's not possible to use a shorter one?

4:29 p.m.

I’m using SDRAM in my design

1

asic destroyer

It's not possible to use a shorter one?

Of course it is. But you'd have to know the pins you could bridge (VCC, VDD, etc.) This thing was made just to fit whatever anyone did, and more to just make something to play with than something that may actually be useful.

Sorry to ask, but why do we need an adapter board?

asic destroyer

Sorry to ask, but why do we need an adapter board?

You don't. This was more of an example for people who get the COB version. Ideally you'd have your own motherboard that did whatever you wanted and just had the mating 70pin mezzanine connector assembled so you could put your chip on however you wanted

1

COB version is a naked chip?

asic destroyer

COB version is a naked chip?

COB (Chip On Board) The COB is the small 14mm x 16mm pcb that is on the top. Your die would be wirebonded to that and then you can do whatever you want after, but don't have to find a way to wirebond yourself as it's not as accessible as PCBA

2

stuart

Click to see attachment 🖼️

How is something like that soldered onto the PCB?

asic destroyer

How is something like that soldered onto the PCB?

That is wirebonded and covered in clear epoxy

Wirebonded from GF?

No they found their own people to do the wirebonding

That means we get such PCB with CHIP (COB)

4:38 p.m.

?

asic destroyer

That means we get such PCB with CHIP (COB)

You get just this part with your die wirebonded and the mezzanine connector on the back. Everything below that (your own motherboard or breakout board) is on you.

1

I that ok to use only this here?

4:42 p.m.

I need short wires for SDRAM

4:43 p.m.

Sorry if I’m asking basic questions. I’m not fully in the loop, and I don’t have much PCB design experience.

For your own die, you can choose whatever pads you want for whatever. These were designed respecting the pad choices chosen by Tiny Tapeout as they had the most ready designs available when we started all this. You're also welcome to design your own COB chip as long as you respect the pad locations on the die, the wirebond pads on the COB PCB, and the location of the mezzanine connector. But going outside the standards will leave all the remaining details to you.

Would it be possible to design one universal board for all designs, despite the SDRAM/SRAM differences and other incompatibilities?

4:51 p.m.

If it’s not possible, I’ll need to ask you more questions here. My assumption is that I’ll need to integrate your COB board via an adapter PCB, considering the Linux SoC’s requirements.

asic destroyer

Would it be possible to design one universal board for all designs, despite the SDRAM/SRAM differences and other incompatibilities?

That's more or less what we have. I am unsure of the exact requirements you're asking for. Maybe there are others here more knowledgable who can answer these questions.

All good. I can handle the schematic, and probably the PCB layout too, otherwise I’ll just ask. I also want to provide three PMOD interfaces so I can connect an SD card, Ethernet, and Flash through them. The board only needs the adapter, SDRAM, discrete components, a clock, uart, and the power supplies. (edited)

1

asic destroyer

All good. I can handle the schematic, and probably the PCB layout too, otherwise I’ll just ask. I also want to provide three PMOD interfaces so I can connect an SD card, Ethernet, and Flash through them. The board only needs the adapter, SDRAM, discrete components, a clock, uart, and the power supplies. (edited)

good old times

5:08 p.m.

maybe 4 pmods: uart, flash, sdcard, ethernet

5:13 p.m.

@Andrew Wingate Last question: do we get the COB with this connector already attached? Which connector we should use for the motherboard?

asic destroyer

@Andrew Wingate Last question: do we get the COB with this connector already attached? Which connector we should use for the motherboard?

Yes

And which Connector 236 or 262? (edited)

asic destroyer

And which Connector 236 or 262? (edited)

Mating connector

1

Thank you @Andrew Wingate

1

5:16 p.m.

I see, that is a pair

Came across another packaging tech, an old one. IBM mst https://www.youtube.com/shorts/MZRlHEyirCE

EvilmonkeyzDesignz

IBM Eagle, a 1 Mebibit RAM chip

4

@RebelMike @psychogenic @Andrew Wingate Hi pros, I have no idea… any advice for me, please?

One more thing I noticed: if an oscillator is used, it has to be an SMD type. According to the dimensions, it still fits underneath the connector. I would have preferred a DIP-4 package so the oscillator could be easily replaced, but it seems I now have to use a 30 MHz SMD oscillator and place it under the connector to keep the trace to the ASIC short. Ideally, the oscillator would have been mounted on top of the connector PCB.

3:26 p.m.

I think you have exactly the same problem. How are you planning to solve it?

I think the first iteration of my host board will have an RP2 on it to allow me to test things and play with the frequency. If I make a standalone version I’d probably go for the chip I mentioned before that buffers the output so trace length isn’t important - or see what other people have done and worked

1

Regardless of the solution, the main challenge is the connector and the placement of the oscillator or crystal. Ideally, the oscillator would be mounted on top of the connector board.

@asic destroyer - At some point I think we will have high quality analog IP for clock generation and we can then get rid of things like external oscillators

1

@Tim 'mithro' Ansell , this COB adapter doesn’t make sense to me for higher frequencies or SDRAM. I talked to Goran—he sees no issue. The solution is to put both the oscillator and SDRAM on the bottom side. My schematic is done; I’ll do the layout in 2–3 months.

8:52 p.m.

I’ll use DIP-8 oscillators, and I want to avoid having any microcontrollers on the board.

asic destroyer

@Tim 'mithro' Ansell , this COB adapter doesn’t make sense to me for higher frequencies or SDRAM. I talked to Goran—he sees no issue. The solution is to put both the oscillator and SDRAM on the bottom side. My schematic is done; I’ll do the layout in 2–3 months.

Tim 'mithro' Ansell

@asic destroyer - At some point I think we will have high quality analog IP for clock generation and we can then get rid of things like external oscillators

AFAIK, you'll always need an external crystal oscillator for accurate clock frequency. I'm not aware of a circuit where oscillation frequency is not dependent on process corner and transistor variations. Alternative is that you need to trim each chip to get wanted clock frequency.

@Chips4Makers aka Staf Verhaegen - Depends on how much accuracy you need. With USB2.0 and a bunch of other protocols you care about the relative drift between two computers and you can get away with using a PLL on the incoming data signals.

@Essen / @Andrew Wingate / @carlfk - https://www.ebay.com/itm/387551726916

EVG GEMINI Automated Production Wafer Bonding System | eBay

Tooled for 200mm Wafer.

2

Tim 'mithro' Ansell

@Essen / @Andrew Wingate / @carlfk - https://www.ebay.com/itm/387551726916

Awesome! For those interested in what wafer bonding is. Asianometry has a video https://youtu.be/2ACiuKgYUkI

Asianometry

Why Wafer Bonding is the Future of Semiconductors

2

asic destroyer

Click to see attachment 🖼️

Andrew Wingate

Awesome! For those interested in what wafer bonding is. Asianometry has a video https://youtu.be/2ACiuKgYUkI

nice

Hello, is it true in my case that the chip will consume 13 mW?

hd@i9:~/hacking/wafer.space/gf180mcu-kianv-rv32ima-sv32/final $ cat metrics.csv  | grep power__tot
power__total,0.013211173005402088

asic destroyer

Hello, is it true in my case that the chip will consume 13 mW?

hd@i9:~/hacking/wafer.space/gf180mcu-kianv-rv32ima-sv32/final $ cat metrics.csv  | grep power__tot
power__total,0.013211173005402088

@Leo Moser (mole99) @Tim 'mithro' Ansell

(edited)

asic destroyer

Hello, is it true in my case that the chip will consume 13 mW?

hd@i9:~/hacking/wafer.space/gf180mcu-kianv-rv32ima-sv32/final $ cat metrics.csv  | grep power__tot
power__total,0.013211173005402088

Most likely not; opensta can use the power information from the liberty file and guess what the power usage would be, but for meaningful real-world numbers you would need to give opensta a VCD or something that contains a realistic trace of what you're going to run. Even so, it will probably barely tickle an ammeter, so don't worry too much.

As a rough upper bound, can we assume a worst case where all transistors toggle every clock cycle?

@Lofty - That was my assumption too, but @Tholin seem to indicate their GF180MCU chips got pretty warm to the touch.

At 50MHz, the AS2650v2 gets hot enough to hurt

2:33 a.m.

I wouldn’t call it "warm" anymore, but firmly in the "hot" territory.

2:34 a.m.

I hope the COB parts will be able to dissipate heat through the PCB ground plane

1

That’s why I cringe a bit when I see people just have CEN permanently selected on the SRAM macros because I’m pretty sure that that is why I have such incredible heat output.

1

That could’ve been communicated beforehand, though.

I still hope that half of that heat output was caravel

Why do you think that?

Because its a whole RISC-V SoC with a bunch of SRAM macros that are also just leaving CEN always active.

1

How was it at 30 MHz? Do you also have data on the heat output, like how much power your design consumed?

At 25MHz, its....fine

1

Do you have data on how much power your board consumed?

No

I have to sleep now. Thanks for the information.

I have no multimeter that doesn’t max out at 100mA

asic destroyer

As a rough upper bound, can we assume a worst case where all transistors toggle every clock cycle?

It's the signals that toggle; if I remember correctly a typical value used for power estimation without a VCD files is using 20% toggle rate on all the signals in a circuit. 100% is really worst case.

1

Essen started a thread. 2025-12-30 7:54 p.m.

asic destroyer

Click to see attachment 🖼️

I don’t know that much about pcb design; for now I’ve got 2-3 months to work on the layout.

asic destroyer

I don’t know that much about pcb design; for now I’ve got 2-3 months to work on the layout.

Pro tip, Order early, order often. JLCPCB and others have this global standard shipping, and it's like $5 US I would order what you have there, just so you can hold it and look at it. Otherwise looks pretty good so far

1

I was thinking we could do the production with Aisler. Since they support open-source projects, it might be a bit cheaper. I’m in Germany as well, so it’d be convenient. Maybe @Tim 'mithro' Ansell , @Matt Venn , or @psychogenic has a contact there and we can do our PCB order through them. (edited)

Andrew Wingate

Pro tip, Order early, order often. JLCPCB and others have this global standard shipping, and it's like $5 US I would order what you have there, just so you can hold it and look at it. Otherwise looks pretty good so far

I have six 100 nF caps on the bottom side for decoupling.

6:06 p.m.

asic destroyer

I was thinking we could do the production with Aisler. Since they support open-source projects, it might be a bit cheaper. I’m in Germany as well, so it’d be convenient. Maybe @Tim 'mithro' Ansell , @Matt Venn , or @psychogenic has a contact there and we can do our PCB order through them. (edited)

IMHO send the draft version to both Aisler and JLC so you can compare

1

I’d also like to have the board assembled.